The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors. An MOS transistor includes a gate electrode as a control electrode and spaced apart source and drain regions between which a current can flow. A control voltage applied to the gate electrode controls the flow of current through a channel between the source and drain electrodes. Complementary MOS (CMOS) devices include a plurality of N-channel MOS (NMOS) transistors and a plurality of P-channel (PMOS) transistors. The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein field effect transistors (NMOS and PMOS transistors) represent one common type of circuit element used in manufacturing such integrated circuit devices.
Numerous processing operations are performed in a very detailed sequence, or process flow, to form such integrated circuit devices, e.g., deposition processes, etching processes, heating processes, masking operations, etc. In general, the formation of integrated circuit devices involves, among other things, the formation of various layers of material and patterning or removing portions of those layers of material to define a desired structure, such as a gate electrode, a sidewall spacer, etc. Etching processes, both wet and dry, are commonly employed to selectively etch one material relative to another material. Certain materials, especially dielectric materials, exhibit a relatively high etch selectivity relative to another material when both materials are exposed to the same etching process. For example, silicon nitride and silicon dioxide are two very common dielectric materials that may be selectively etched relative to one another using the appropriate etch chemistries, wherein the silicon nitride is removed and the silicon dioxide is only slightly etched, or vice versa. For example, silicon nitride may be selectively etched relative to silicon dioxide by performing a wet etching process using hot phosphoric acid as the etchant.
The formation and/or removal of sidewall spacers is a common situation where silicon nitride is etched relative to an underlying layer of silicon dioxide, or vice versa. In one example, a relatively thin silicon dioxide liner layer is formed over a gate electrode structure of a transistor and a silicon nitride layer is then formed on the silicon dioxide liner layer. In some process flows, it is desirable to remove the silicon nitride from top portions of the gate electrode structure to form a silicon nitride spacer structure. In other process flows, it is desirable to remove the silicon nitride from the sidewalls of the gate electrode structure while leaving the silicon nitride layer in place along horizontal surfaces of the gate electrode structure and the substrate. Regarding the former, many etching technologies are well-known in the art that allow for horizontal surfaces of the silicon nitride to be etched relative to the vertical surfaces, thereby forming the sidewall spacers. Regarding the latter, however, in order to etch the silicon nitride from the vertical sidewalls only, additional steps of depositing and patterning a masking layer over the horizontal surfaces must be used in order to prevent the silicon nitride from being etched form the horizontal surfaces at the same time as the sidewalls. These additional depositing/patterning steps require additional time, equipment, and expense to complete, thus increasing the overall cost of fabricating the integrated circuit.
Accordingly, it is desirable to provide improved methods for etching dielectric materials in the fabrication of integrated circuits. Furthermore, it is desirable to provide methods for etching one dielectric material selective to another dielectric material along vertical sidewalls of a gate electrode structure that do not require additional masking/patterning steps. Still further, other desirable features and characteristics of the present disclosure will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.